1. Field of Invention
The present invention relates to a high performance thermally enhanced package. More particularly, the present invention relates to a high performance thermally enhanced package with a cavity type heat sink therein and a method of fabricating the same.
2. Description of Related Art
In this information conscious society, multi-media applications are developed at a tremendous pace. To complement this trend, integrated circuit packages inside electronic devices must match a set of corresponding demands for digital input, networking, local area connection and personalized usage. In other words, each electronic device must be highly integrated so that more powerful programs can be executed at a higher speed and yet each package has to occupy less space and cost less. Due to the miniaturization and densification of integrated circuit packages, most packages have an edge length only 1.2 times the encapsulated chip or a package area 1.25 times the chip area. Hence, each package is able to provide powerful functions within a very small area. Furthermore, each chip package can be easily mounted on a printed circuit board using standard surface mount technology (SMT) and common equipment. Therefore, chip packages are mostly welcomed by the industry. The most common types of chip packages include bump chip carrier (BCC) package, quad flat nonleaded (QFN) package and lead frame type package.
FIG. 1 is a schematic cross-sectional view of a conventional bump chip carrier package. As shown in FIG. 1, the bump chip carrier (BCC) package mainly comprises a silicon chip 110, a layer of adhesive glue 104, a plurality of bonding wires 106, a plurality of terminals 108 and a plastic package body 110. The chip 100 has a plurality of bonding pads 102 on its front surface and contains a layer of adhesive glue 104 on its back surface. The bonding pads 102 on the chip 100 are electrically connected to the terminals 108 through the bonding wires 106. The plastic package body 110 encapsulates the chip 100 and the bonding wires 106. In addition, the adhesive glue 104 at the back surface of the chip 100 is exposed outside the plastic body 110. Through the terminals 108, the chip 100 can communicate electrically with other electronic devices or a host board. However, to produce this type of package structure, an etching operation is needed to expose the adhesive glue 104 at the back of the chip 100 and shape the terminals 108. Hence, the structure is a bit complicated to fabricate.
FIG. 2 is a schematic cross-sectional view of a conventional quad flat nonleaded package. As shown in FIG. 2, the quad flat nonleaded (QFN) package mainly comprises a chip 200, a layer of adhesive glue 204, a plurality of bonding wires 206a, a plurality of bonding wires 206b, a lead frame 208 and a plastic package body 210. The lead frame 208 has a die pad 208a and a plurality of leads 208b. The chip 200 has a plurality of bonding pads 202 on the upper surface. The back surface of the chip 200 is attached to the die pad 208a through the adhesive glue layer 204. A portion of the bonding pads 202 on the upper surface of the chip 200 are electrically connected to the leads 208b through respective bonding wires 206b. Meanwhile, another portion of the bonding pads 202 on the upper surface of the chip 200 is electrically connected to the die pad 208b (normally ground pads) through respective bonding wires 206a. The plastic package body 210 encapsulates the chip 200, the adhesive glue 204 and the bonding wires 206a, 206b such that one side of the die pad 208a and the leads 208b are exposed. The exposed surface of the die pad 208a increases the heat dissipating capacity of the package while the exposed leads 208b facilitate electrical connection with other devices or a host board.
FIG. 3 is a schematic cross-sectional view of a conventional lead frame type of package. As shown in FIG. 3, the lead frame type package mainly comprises a chip 300, a layer of adhesive glue 304, a plurality of bonding wires 306, a lead frame 308 and a plastic package body 310. The lead frame 308 has a die pad 308a and a plurality of leads 308b. The upper surface of the chip 300 has a plurality of bonding pads 302 thereon. The back surface of the chip 300 is attached to the die pad 308a through the layer of adhesive glue 304. The bonding pads 302 on the chip 300 are electrically connected to the leads 308b through the bonding wires 306. The plastic package body 310 encapsulates the chip 300, the adhesive glue 304, the bonding wires 306, the die pad 308a and a portion of the leads 308b. Thus, the leads 308b exposed outside the package body 310 can be electrically connected with other carriers. Heat generated by the package is channeled outside through the leads or an externally attached heat sink. Consequently, heat dissipation capacity for this type of package is usually low.
All the aforementioned packages have a so-called wire-bonding chip design. In other words, the chip is electrically connected to the package through bonding wires. Bonding wires not only increase overall thickness of a package, but also increase overall circuit path compared with a conventional flip-chip packaging technique. Moreover, to package a wire-bonding chip into a flip-chip package, a wiring redistribution is required. After the redistribution process, overall circuit length will be increased so that a parasitic inductance problem may crop up.